Most microcontroller and microprocessor devices include bus interfaces to communicate with off-chip peripheral devices. These bus interfaces support a wide assortment of products including memories, analog to digital converters, digital to analog converters, liquid crystal display (LCD) controllers and a myriad of other peripheral devices.
There are a number of different peripheral bus interfaces that have unique characteristics targeting specific categories of peripheral devices. The available bus interfaces in the prior art try to balance bus performance with implementation cost. Host microcontroller implementation cost covers a number of characteristics including interface signal count, the physical characteristics of the I/O drivers and complexity of the bus controller integrated into the microcontroller.
There is often a balancing act between the number of pins required and the level of performance provided by the peripheral bus. More specifically, bus interfaces typically focus on either minimizing pin count or maximizing data throughput. On the one hand, higher latency busses are often implemented with fewer bus signals to minimize system level hardware overhead. For instance, serial peripheral bus interfaces typically are designed with low pin counts, but have slower data rates. As an example, the I2C bus is a low speed interface that requires only two pins to support communication between the host device and a peripheral device. On the other hand, low-latency and high-throughput peripheral busses typically require a large number of signals to support the interface between a host microcontroller and peripheral device. For instance, parallel peripheral bus interfaces are designed for high speed data transmission rates. As an example, Dynamic Random Access Memory (DRAM) bus interfaces are used to provide high data throughput to off-chip DRAM memory devices.